riporto un commento di justmeee su XBH
Most of the Good osc have a toleranz of 250 ppm. What could be very much. You have to count the Ticks of 0xDA and then calculate the glitch Point based on this. Maybe this is what TX will so with the CR3. I noticed that Even a reset Pulse of 1 Tick could be to Long. Something changed inside the reset circuit in the CPU. The Trinity has a resistance of 1,2kohm compared to 70 kohm on the corona.
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