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Discussione: Jasper segnale com assente..niente cpu key

  1. 19-10-13 #1
    criminalce
    criminalce è offline
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    Jasper segnale com assente..niente cpu key

    Buongiorno a tutti.
    Qualcuno potrebbe confermarmi se il log di seguito è giusto per un corretto glitch...?
    Codice:
    Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post C9 
Post E9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F8 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post E9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post C9 
Post F9 
Post D9 - SHA_COMPUTE_CB_B 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post E9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post FC 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post FC 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post FD 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post FC 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F4 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post C9 
Post F9 
Post D9 - SHA_COMPUTE_CB_B 
Post F9 
Post C9 
Post F9 
Post C9 
Post E9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post C9 
Post F9 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 41 - VERIFY_OFFSET 
Post 44 - FETCH_CONTENTS 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE
    [URL=http://imageshack.us/photo/my-images/30/t5cp.png/][/URL]

    [URL=http://imageshack.us][/URL]
    Praticamente cerco di estrarre la Key tramite squirter come ho fatto tante altre volte ma non risulta nessun segnale sul monitor com...
    Ultima modifica di criminalce; 19-10-13 alle 09: 31

  2. 19-10-13 #2
    criminalce
    criminalce è offline
    Membro
    Data Registrazione
    Jan 2012
    Località
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    Messaggi
    95
    Nessun suggerimento??...è la prima volta che mi tocca rinunciare su una console che glitcha...
  3. 19-10-13 #3
    Razorbacktrack
    Razorbacktrack è offline
    The Banhammer! L'avatar di Razorbacktrack
    Data Registrazione
    Jul 2011
    Località
    Catania
    Messaggi
    8,950
    Niente up prima delle 24h,se non ti rispondono aspetti .
  4. 19-10-13 #4
    criminalce
    criminalce è offline
    Membro
    Data Registrazione
    Jan 2012
    Località
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    Messaggi
    95
    si può chiudere; ho risolto....era un problema hardware mio...il pc pur rilevando lo squirter come porta com, ha deciso di punto in bianco di non acquisire più segnale...

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