Ciao a tutti ho una Jasper 16Mb con dashboard 2.0.16537 a cui ho montato la R-Jtag, ma non ne vuole sapere di far avviare Xell.
Ho estratto la nand con AutoGG 0.9.3 utilizzando il programmatore PIC18F2455 (nessun bad-block).
Ho creato xell con J-Runner 0.3 spuntando su JTAG, R-Jtag e Aud_Clamp e mi ha creato il file "jasper_hack_aud_clamp.bin" successivamente l'ho scritto con NandPro 2.0e.
Montato l'R-Jtag i DIP sono 7,8,5 ON e la tensione è di default.
Per la QSB ho ponticellato 1-3 e collegato il filo al Q2N1, primo switch su ON mentre il secondo switch al centro, per la resistenza ho messo 470.
Questo è il risultato del CR3 Pro Rater.
Codice HTML:Phat Selected Version: 10 Power Up Waiting for POST to change Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 7F Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post E0 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL Post 12 - FSB_CONFIG_RX_STATE Post 13 - FSB_CONFIG_TX_STATE Post 14 - FSB_CONFIG_TX_CREDITS Post 15 - FETCH_OFFSET Post 16 - FETCH_HEADER Post 17 - VERIFY_HEADER Post 18 - FETCH_CONTENTS Post 19 - HMACSHA_COMPUTE Post 1A - RC4_INITIALIZE Post 1B - RC4_DECRYPT Post 1C - SHA_COMPUTE Post 1D - SIG_VERIFY Post 1E - BRANCH Post 20 - CB entry point reached Post 21 - INIT_SECOTP Post A0 - Panic - VERIFY_SECOTP_6 Most Fails(cumulative): 0xA0 Shutdown
Segnalibri